The present invention relates to a construction of a channel region of an insulating gate field effect transistor (hereinafter referred to as a MISFET) constituting a semiconductor device of an integrated circuit and more particularly to a semiconductor device in which a surface inversion voltage (threshold voltage) of the channel region which is determined by impurity concentrations and thicknesses of a gate insulating film of the channel region is controlled.
The present invention relates to a semiconductor device of an integrated circuit composed of MISFETs having a plurality of threshold voltages formed on the same substrate and to a manufacturing method thereof.
The present invention also relates to a semiconductor device of an integrated circuit having different conductive MISFETs on the same substrate and to a manufacturing method thereof.
The present invention further relates to a semiconductor device of an integrated circuit having high withstand voltage and low voltage MISFETs to which different gate voltages are applied on the same substrate and to a manufacturing method thereof.
The present invention furthermore relates to a semiconductor device comprising an analog circuit formed and a digital circuit on the same substrate and to a manufacturing method thereof.
The present invention relates additionaly to a semiconductor device formed on a thin film semiconductor provided on an insulating layer and to a manufacturing method thereof.
FIGS. 38A through 38C are schematic plan views representing MISFETs within a prior art semiconductor device of an integrated circuit.
Note that the explanation of the present specification is made exemplifying a MOSFET in which an insulating layer interposed between a metal gate electrode and a semiconductor substrate is a silicon oxide film, as a typical example of the MISFET.
FIGS. 38A to 38C schematically show a source, drain and gate of three kinds of transistors, and aluminum metallic wirings and other elements are omitted to simplify the description.
Transistors 1, 2 and 3 have each different threshold voltage (VTH).
FIG. 39 is a schematic section view illustrating the MOSFET within the prior art semiconductor integrated circuit.
In the transistor 1, an impurity concentration of a channel region 4004 is set at a value of an impurity concentration of a semiconductor substrate 4006 and a threshold voltage determined by the impurity concentration of the channel region 4004 and a thickness of a gate insulating film 4005 is denoted as VTH1.
When it is desired to differentiate a threshold voltage VTH2 Of the second transistor 2 from VTH1, a channel region 2 having an impurity concentration which is different from that of the channel region 1 of the transistor 1 is formed by optically patterning a photoresist by using a glass mask and others for selecting a region to which an impurity is doped (photolithographic technique) and by doping the impurity via the gate insulating film 4005 by ion implantation and others using the photoresist selectively formed as a mask.
At this time, a pattern 3905 of the glass mask 1 for ion implantation for selecting the region to which the impurity is doped is created so as to be slightly larger than the channel region to cover the whole surface thereof considering a dislocation of registration of the glass mask as shown in FIG. 38B and the photoresist is removed slightly more than the channel region to dope the impurity to the channel at the region where the photoresist is removed.
The gate insulating film 4005 is normally formed of a silicon oxide film having a homogeneous thickness from around 10 nm to 100 nm.
By constructing as described above, the transistor 2 having VTH2 which is different from VTH1 of the transistor 1 may be formed. In the same manner, a transistor having a necessary threshold voltage may be formed by doping a necessary impurity like VTH3 of the transistor 3.
Further, although not shown in the figure, in a semiconductor device of an integrated circuit in which a high voltage MOSFET having a thick gate oxide film and a low voltage MOSFET having a thin gate oxide film are provided on the surface of the same substrate, a concentration of a homogeneous impurity region of channel region of each MOSFET is controlled by a photolithographic technique in order to equalize each threshold voltage to almost the same value.
Similarly, in a CMOS type integrated circuit comprising P-type and N-type MOSFETs, threshold voltages are equalized to almost the same value by separate impurity doping processes.
However, because the MOSFETs within the prior art semiconductor device of the integrated circuit have the channel region having the homogeneous impurity concentration and the gate insulating film having the uniform thickness as described above, the surface inversion voltage of the channel becomes constant and hence processes for doping a necessary number of types of impurities or impurity concentrations to the channel region have been necessary in order to form transistors having a plurality of types of threshold voltages within the semiconductor device of the integrated circuit formed on a single semiconductor substrate.
Accordingly, it has been costly and been a restriction in designing the circuit to form the transistors having the plurality of types of threshold voltages within the semiconductor device of the integrated circuit formed on single semiconductor substrate.
Further, a plural number of photolithographic processes have been necessary to adjust the threshold voltages matching with the range of the power supply voltage in the semiconductor device of the integrated circuit in which transistors having a structure in which threshold voltages differ before an impurity is doped to the channel region are provided on the same substrate. Accordingly, a manufacturing period has been prolonged and a manufacturing cost has been increased to manufacture the semiconductor device in which the threshold voltages of the MOSFETs having different gate insulating films, different substrate concentrations or different conductive types are controlled.
In order to solve the aforementioned problems, the present invention adopts the following means.
As first means, channel regions having different surface inversion voltages such that the channel surface is inverted by more than two different gate voltages are provided within the same channel of a MOSFET.
Further, plural types of ratios of plane areas of a first surface inversion voltage area and a second surface inversion voltage region or plural types of individual plane size or shape of the first surface inversion voltage region and the second surface inversion voltage region are provided.
As second means, the second surface inversion voltage region is divided into a plurality of plane shapes.
There are the following methods as examples of the method of dividing the region into the plurality of plane shapes:
1) divide in strips parallel to the direction of the channel length;
2) divide in strips parallel to the direction of the channel width;
3) divide in dots; and
4) divide in checker pattern.
As third means, the channel region having more than two different surface inversion voltages is obtained by forming regions having more than two different impurity concentrations (channel impurity region) on the surface of the same channel region of the MOSFET.
As fourth means, the channel impurity region described in the third means is formed to be shallower than a depth of junction of the source and drain regions.
As fifth means, a first MOSFET and a second MOSFET each having a gate insulating film formed with different thicknesses are formed and the first through fourth means described above are applied to each of them.
As sixth means, a first MOSFET is formed on a first conductive semiconductor substrate and a second MOSFET is formed within a well region having a different impurity concentration from that of the semiconductor substrate but formed in the same conductive type with that, and first through fourth means described above are applied to each.
As seventh means, a first MOSFET is formed on a first conductive semiconductor substrate and a second MOSFET is formed within a well region formed with a different conductive type from that of the semiconductor substrate, and first through fourth means described above are applied to each.
As eighth means, a MOSFET is formed on a thin film semiconductor whose thickness is thinner than 1Om and which is formed on the insulating layer, and the first through fourth means described above are applied to the MOSFET.
As ninth means, the thickness of the thin film semiconductor layer described in the eighth means is equalized to a thickness of a channel region of the MOSFET formed on the thin film semiconductor layer.
As tenth means, the thickness of the thin film semiconductor layer described in the eighth means is equalized to a depth of a channel impurity region of the channel region of the MOSFET formed on the thin film semiconductor layer.
As 11-th means, a semiconductor device is provided in which a first conductive impurity is doped without using a photoresist pattern as a mask in doping the impurity in an enhancement type MOSFET channel region and then a second conductive impurity is doped only to a channel region of a depletion type MOSFET by using the photoresist as a mask so that a peak thereof comes to a position within xc2x120 nm from a peak position of the first conductive impurity profile.
As 12-th means, a semiconductor device is provided in the semiconductor device in the 11-th means described above in which a photoresist is formed selectively and partially on the depletion type MOSFET channel region and then the second conductive impurity is doped only to the channel region of the depletion type MOSFET by using the photoresist as a mask so that a peak thereof comes to a position within xc2x120 nm from a peak position of the first conductive impurity profile.
As 13-th means, a manufacturing method of a semiconductor device is taken, comprising steps of:
forming a field insulating film on the surface of a first conductive semiconductor region on the surface of a substrate;
forming a gate insulating film on the surface of a first transistor region and second transistor region of the semiconductor region;
forming a photoresist pattern for forming a channel impurity region on the surface of the first transistor region;
forming the channel impurity region by doping an impurity on the surface of the first transistor region by using the resist pattern as a mask;
patterning a gate electrode on the gate insulating film;
forming a second conductive source and drain regions on the surface of the first transistor region so that they are partitioned by the gate electrode;
forming an intermediate insulating film on the gate electrode;
forming contact holes through the intermediate insulating film; and
patterning metallic wirings so as to be overlaid on the contact holes;
at least a plurality of first impurity concentration regions and second impurity concentration regions being divided and formed in plane between the source region and the drain region in the channel impurity forming region.
As 14-th means, a manufacturing method of the semiconductor device wherein the first impurity concentration region and second impurity concentration region are formed by selectively doping an impurity for controlling threshold voltage within the same channel by forming the photoresist in a desired shape on the region to be formed as the channel is taken.
As 15-th means, a manufacturing method of the semiconductor device wherein the first impurity concentration region and second impurity concentration region are formed by selectively doping an impurity for controlling threshold voltage within the same channel by ion implantation by forming the photoresist in a desired shape on the region to be formed as the channel is taken.
As 16-th means, a manufacturing method of the semiconductor device is taken, comprising steps of forming a first gate insulating film on the first transistor region and forming a second gate insulating film having a thickness different from that of the first gate insulating film on the second transistor region, and in which the 13-th to 15-th means described above are applied to each of the first transistor region and the second transistor region.
As 17-th means, a manufacturing method of the semiconductor device is taken, comprising steps of forming a second conductive well region on the surface of the first conductive semiconductor region containing the source and drain regions of the first transistor region, doping a first conductive impurity as the source and drain regions of the first transistor region and doping a second conductive impurity as the source and drain regions of the second transistor region, and in which the 13-th to 15-th means described above are applied to each of the first transistor region and the second transistor region.
As 18-th means, a manufacturing method of a semiconductor device is taken in which a first conductive impurity is doped without using a photoresist pattern as a mask in doping the impurity in an enhancement type MOSFET channel region and then a second conductive impurity is doped only to a channel region of a depletion type MOSFET by using the photoresist as a mask so that a peak thereof comes to a position within xc2x120 nm from a peak position of the first conductive impurity profile.
As 19-th means, a manufacturing method of a semiconductor device is taken in the semiconductor device in the 18-th means described above in which a photoresist is formed selectively and partially on the depletion type MOSFET channel region and then the second conductive impurity is doped only to the channel region of the depletion type MOSFET by using the photoresist as a mask so that a peak thereof comes to a position within xc2x120 nm from a peak position of the first conductive impurity profile.
As 20-th means, the channel region having more than two different surface inversion voltages is obtained by forming a gate insulating film having more than two different thicknesses on the same channel region of the MOSFET.
As 21-st means, a manufacturing method of a semiconductor device is taken, comprising steps of:
forming a field insulating film on the surface of a first conductive semiconductor region on the surface of a substrate;
forming a photoresist for selecting a region for forming a gate insulating film having different thicknesses on the surface of a first transistor region and second transistor region of the semiconductor region;
forming the gate insulating film having different thicknesses in response to the shape of the photoresist;
forming a channel impurity region on the surface of the first and second transistor regions;
patterning a gate electrode on the gate insulating film;
forming second conductive source and drain regions on the surface of the first transistor region so that they are partitioned by the gate electrode;
forming an intermediate insulating film on the gate electrode;
forming contact holes through the intermediate insulating film; and
patterning metallic wirings so as to be overlaid on the contact holes;
the gate insulating film being divided to form at least a plurality of regions of gate insulating film having the first thickness and the second thickness in plane between the source and drain regions on the same channel.
As 22-nd means, a manufacturing method of the semiconductor device wherein the gate insulating film having more than two different thicknesses is formed by forming a photoresist selectively on the same channel and by selectively removing or forming the gate insulating film by using the photoresist selectively formed as a mask is taken.
As 23-rd means, a semiconductor device is provided wherein an analog circuit comprising the MISFET described in the first through 12-th means and 20-th means and a digital circuit comprising a second MISFET having a second channel region whose region is smaller than the channel region of the MOSFET used in the analog circuit by more than one digit are provided on the surface of the semiconductor substrate.
As 24-th means, a plurality of the MISFETs described in the first through 12-th means and the 20-th means are diode-connected in series to construct a voltage boosting circuit (charge pump circuit) in which a capacitor for storing charges is connected to each of the MISFETs and the area ratio or shape of the second surface inversion voltage region is changed as along the steps of the voltage boosting circuit from the previous ones to the rear ones.
The voltage boosting circuit is mounted in the semiconductor device of the integrated circuit having a non-volatile semiconductor memory device.
As 25-th means, the MOSFET described in the first to 12-th means and the 20-th means is used in a differential amplifier circuit.
As 26-th means, the MOSFET described in the first to 12-th means and the 20-th means is used in a reference voltage generating circuit for generating a constant voltage which becomes a criterion for comparing voltages in the differential amplifier circuit.
As 27-th means, the differential amplifier circuit described in 25-th means is connected to the reference voltage generating circuit described in the 26-th means and to an output circuit for generating an output a voltage to construct a semiconductor device of an integrated circuit which always outputs a constant output voltage even if a load of the output is changed by comparing a voltage generated in the reference voltage generating circuit with the voltage outputted to the outside of the output circuit or a voltage which follows the voltage outputted to the outside with a predetermined ratio by the differential amplifier circuit.
A threshold voltage VTH of the insulating gate field effect transistor (MISFET) may be represented by the following equation:                               V          TH                =                              Φ            MS                    +                                    Q              B                                      C              OX                                +                      2            ⁢                          Φ              f                                                          (        1        )            
where, "PHgr"MS is a difference in work function between the substrate and the gate electrode, QB is a depletion charge amount per unit area generating in the channel region, COX is a capacitance per unit area of the gate insulating film and "PHgr"f is the Fermi level of the substrate.
The whole threshold voltage VTH when a plurality of areas having threshold voltages which differ locally, i.e. surface inversion voltages VT1 and VT2, are provided within the channel region is represented by the following equation:
VTH=AVT1+BVT2xe2x80x83xe2x80x83(2)
A and B are constants of 0xe2x89xa6A and Bxe2x89xa61 and depend on the shape of pattern of each area.
Accordingly, the areas having the plural threshold voltages may be formed on the same substrate by one set of photolithography by controlling the constants A and B by the photolithographic technique. However, VTH is always set between each local threshold voltages, like VT1xe2x89xa6VTHxe2x89xa6VT2. The local threshold voltage is a threshold voltage which does not depend on the channel size when the channel region is formed with a homogeneous impurity concentration (a transistor having a very large size) and is a value derived mathematically from Equation (1).
Further, a target threshold voltage may be achieved by one set of photolithography steps in a MOS transistor having different gate insulating film capacitance (or thicknesses and types of gate insulating films), substrate concentrations or "PHgr"MS by patterning locally different impurity regions on the channel region.
That is, when the different impurity regions are patterned, the threshold voltage is approximated by the following equation:                               V          TH                =                              Φ            MS                    +                      α            ·                                          Q                B1                                            C                OX                                              +                      β            ·                                          Q                B2                                            C                OX                                              +                      2            ⁢                          Φ              f                                                          (        3        )            
Alpha and beta are constants of 0xe2x89xa6xcex1+xcex2xe2x89xa61. QB1 and QB2 are depletion charge amounts per unit area in the direction of channel depth along the direction of depth of the substrate from the surface of the channel region of each different impurity region. "PHgr"MS and "PHgr"f are effective values which can be found substantially by experiments because a plural types of impurity concentrations and plural areas exist in the channel region.
By Equation (3), threshold voltages may be controlled to almost the same value by one kind of photolithography in each transistor having different gate insulating films for example by patterning the impurity in the channel region.
Furthermore, threshold voltages may be controlled to almost the same value toward the enhancement side by the similar means in both N-type and P-type MISFETs provided on the same substrate.
While Equation (1) shows that the threshold voltage will change even when a capacitance per unit area of the gate insulating film is changed, it also shows that the threshold voltage will change similarly also when plural types of plural areas in which thicknesses of the gate insulating film differ exist within one channel even when the impurity concentration of the channel region is constant.
The threshold voltage at this time may be approximated by the following equation:                               V          TH                =                              Φ            MS                    +                      α            ·                                          Q                B                                            C                OX1                                              +                      β            ·                                          Q                B                                            C                OX2                                              +                      2            ⁢                          Φ              f                                                          (        4        )            
Alpha and beta are constants of 0xe2x89xa6xcex1+xcex2xe2x89xa61, similarly to Equation (3). QB is a depletion charge amount per unit area in the direction of channel depth along the direction of depth of the substrate from the surface of the channel region. COX1, and COX2 are values of capacitance per unit area of the gate insulating film having locally different thicknesses.
The operations of the present invention will be shown below along the items described in Means for Solving the Problems.
By taking the first means, a transistor having a plurality of threshold voltages may be obtained within the same semiconductor device of an integrated circuit.
Thereby, a degree of freedom in designing the circuit is increased and a very high performance and high function semiconductor integrated circuit device may be realized at low cost.
By taking the second means, a transistor having such good characteristics in that there is no kink and less leak current may be obtained as aimed at in relatively high accuracy. It also allows one to obtain better characteristics by dividing finely within a range permitted by fine processing.
By taking the third and fourth means, a transistor having a plurality of threshold voltages may be readily obtained by one time of channel impurity doping process.
Heretofore, although only two types of transistors in which an impurity is doped to the whole channel region and in which no impurity is doped at all are created as for the threshold voltages of the MOSFET formed on the same conductive semiconductor substrate region or well region in controlling the threshold voltages of the MOSFET by a channel impurity doping process comprising one time of photoresist optical patterning process and ion implantation process for example, a transistor having at least three types of threshold voltages may be formed by taking the third and fourth means because the threshold voltage of the transistor in which the impurity is doped partially to the channel region is distributed between the threshold voltage of the transistor in which the impurity is doped to the whole channel region and that of the transistor in which no impurity is doped.
Further, a transistor having more than three types of threshold voltages may be readily formed by adequately selecting an area ratio and shape of the area to which the impurity is doped.
By taking the fifth means, transistors in which the threshold voltages are equal or are adjusted to desired values, respectively, may be readily obtained even if the thickness of the gate insulating film differ by one time of channel impurity doping process.
By taking the sixth means, transistors in which the threshold voltages are equal or are adjusted to desired values, respectively, may be readily obtained even if they are formed in the same conductive region having different impurity concentrations of the substrate or well by one time of channel impurity doping process.
By taking the seventh means, transistors in which the threshold voltages are equal or are adjusted to desired values, respectively, may be readily obtained even if they are formed on different conductive substrates or well regions by one time of channel impurity doping process.
By taking the eighth, ninth and tenth means, a plurality of transistors having different threshold voltages may be readily obtained by one time of channel impurity doping process in transistors formed on a thin film semiconductor layer on an insulating layer.
When the thickness of the thin film semiconductor layer is sufficiently thin and is equal to the thickness of the channel region of the transistor or to the depth by which the channel impurity is doped, transistors having better characteristics may be obtained because the channel impurity partially doped fully diffuses, approaching to a more homogeneous concentration as a whole.
By taking the 11-th means, one process of the optical patterning processes of the photoresist may be omitted.
By taking the 12-th means, one process of the optical patterning processes of the photoresist may be omitted and the MOSFET having more than three types of desired threshold voltages from enhancement type to depletion type may be formed by one time of photoresist optical patterning process and two times of impurity doping processes.
By taking the 13-th through 17-th means, the MOSFET described in the third through tenth means and a semiconductor integrated circuit device carrying the MOSFET described above may be easily manufactured without adding a special process, as compared to the prior art method.
By taking the 18-th means, a semiconductor device may be manufactured without degrading the characteristics of the MOSFET even if one process of the photoresist optical patterning processes is omitted.
By taking the 19-th means, one process of the optical patterning processes of the photoresist may be omitted and a MOSFET having more than three types of desired threshold voltages from enhancement type to depletion type may be formed by one time of photoresist optical patterning process and two times of impurity doping processes.
By taking the 20-th means, a MOSFET having a plurality of threshold voltages may be readily obtained just by adding one process for forming a gate insulating film having a second thickness.
Further, a MOSFET having a plurality of threshold voltages may be readily obtained without adding new process when there has been a process for forming the gate insulating film having the second thickness such as a tunnel insulating film like a semiconductor device of an integrated circuit carrying a FLOTOX type non-volatile memory.
By taking the 21-st and 22-nd means, the MOSFET described in the 20-th means and a semiconductor device of an integrated circuit carrying the MOSFET may be easily manufactured.
By taking the 23-rd means, a high performance analog circuit having a large degree of freedom may be structured for a transistor of the analog circuit having relatively large channel region by forming the channel impurity region into an adequate shape and size, and the analog circuit and a digital circuit may be carried on the same substrate at low cost.
By taking the 24-th means, a very efficient voltage boosting circuit may be structured because a voltage drop caused by an increase of threshold voltage due to a substrate effect in a plurality of MOSFETs connected in series (MOS diode) may be reduced.
Further, a low cost and high performance semiconductor device of an integrated circuit may be realized when the voltage boosting circuit in the 24-th means is mounted on the semiconductor integrated circuit device having a non-volatile memory function because a circuit having the same boosting ability may be constructed with a circuit having less area or a circuit having a high boosting ability may be constructed by a circuit having the same area.
By taking the 25-th, 26-th and 27-th means, a low cost semiconductor device of an integrated circuit may be realized because the separate processes for doping impurities to form a MOSFET having a plurality of threshold voltages in the prior art may be realized by one process. The detailed explanation thereof is given in the following Detailed Description of Preferred Embodiments.